Digital Verification Engineer
With more than 50 years of experience developing advanced semiconductor technology and application specific algorithms, Allegro MicroSystems is a global leader in power and sensing solutions. From green energy to advanced mobility and motion control systems, our team is passionate about developing intelligent solutions that move the world forward and give our customers a competitive edge.
At Allegro MicroSystems, we’re passionate about developing intelligent solutions that move the world toward a safer and more sustainable future – while giving our customers a competitive edge.
Our global engineering, manufacturing and support, combined with our agility, make Allegro a trusted partner to both large enterprises and regional market leaders worldwide.
Allegro Microsystems, LLC is a leading provider of linear and angle measurement and current sensing precision analog multi-mode sensors. The company’s products form the building blocks of increasingly intelligent automotive sensing applications, enabling advancements in controllability, efficiency, and safety, in the transportation development industry. With a portfolio of intellectual property and a rich history of design and process innovation, Allegro is a trusted partner to leading companies in some of the world’s largest markets to include consumer, industrial, and automotive sensors.
You will be part of a new verification team which collaborates on the verification of embedded SoCs based on innovative new core architectures. As a member of the digital development team, you will be responsible for developing verification plans based on microarchitecture specifications and using SV/UVM based verification environments to meet the required coverage metrics.
- Review and analysis of IP and system-level design specifications to drive identification of functional coverage conditions.
- Propose and implement appropriate verification solutions to meet functional coverage requirements.
- Verilog/SystemVerilog/UVM testbench development.
- Code and functional coverage analysis and debug of RTL and gate-level simulations.
- Maintenance and continuous improvement of verification methodology, automation and regression control.
Skills and Qualifications
- Knowledge of the embedded SoC design and verification life-cycle with an emphasis on design verification tasks such as: test plan development, test bench creation, test coverage analysis and debug of unexpected design behavior.
- Knowledge of CPU, Memory or I/O Subsystem microarchitectures (caches, virtual memory, DMA, memory access optimizations).
- Experience identifying functional coverage conditions based on microarchitecture specifications.
- Experience of SystemVerilog digital & mixed-signal verification.
- Experience of script generation for processing results as well as regression control configuration
- Experience of constrained random verification.
- Experience of bus-functional model development for verification of custom or industry-standard interfaces.
- Strong skills in UVM testbench development.
- Languages: SystemVerilog, Verilog, C, ASM
- Scripting: Python, Perl
- Familiarity with Cadence toolsets.
- Knowledge of digital design techniques
- Knowledge of the overall front-to-back digital design flow.
- Good verbal and written communication skills
- Ability to work in a multi-cultural team environment
- Good presentation skills in English and the ability to present information in a clear and concise manner
- A high level of commitment and self-motivation
- The ability to work as part of a world-wide development team with diverse engineering disciplines
- Competitive salaries
- Recognition awards
- Mentorship from senior engineers and managers
- Flexible working hours
- English language courses
- Meal vouchers and flexi passes
- Contribution to personal pension insurance
- Great working environment with coffee and tea as you wish
- Life insurance plan
- Gym membership contribution